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14-bit, 1 msps, unipolar/bipolar programmable input pulsar ? adc data sheet ad7951 rev. a document feedbac k information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2006C2012 analog devices, inc. all rights reserved. technical suppor t www.analog.com features multiple pins/software programmable input ranges: 5 v, 10 v, 5 v, 10 v pins or serial spi? compatible input ranges/mode selection throughput 1 msps (warp mode) 800 ksps (normal mode) 670 ksps (impulse mode) 14-bit resolution with no missing codes inl: 0.3 lsb typ, 1 lsb max (61 ppm of fsr) snr: 85 db @ 2 khz i cmos? process technology 5 v internal reference: typical drift 3 ppm/c; temp output no pipeline delay (sar architecture) parallel (14- or 8-bit bus) and serial 5 v/3.3 v interface spi-/qspi?-/microwire?-/dsp-compatible power dissipation: 10 mw @ 100 ksps 235 mw @ 1 msps 48-lead lqfp and lfcsp (7 mm 7 mm) packages applications process control medical instruments high speed data acquisition digital signal processing instrumentation spectrum analysis ate general description the ad7951 is a 14-bit, charge redistribution, successive approximation register (sar) architecture analog-to-digital converter (adc) fabricated on analog devices, inc.s i cmos high voltage process. the device is configured through hardware or via a dedicated write only serial configuration port for input range and operating mode. the ad7951 contains a high speed 14-bit sampling adc, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. a falling edge on cnvst samples the analog input on in+ with respect to a ground sense, in?. the ad7951 features four different analog input ranges and three different sampling modes: warp mode for the fastest throughput, normal mode for the fastest asynchronous throughput, and impulse mode where power is scaled with throughput. operation is specified from ?40c to +85c. functional block diagram 06396-001 14 control logic and calibration circuitry clock ad7951 dgnd dvdd avdd agnd ref refgnd in+ pd reset cnvst pdbuf refbufin pdref ref temp d[13:0] busy rd cs ob/2c ognd ovdd byteswap ser/par ref amp serial data port parallel interface switched cap dac v cc v ee warp impulse bipolar ten serial configuration port in? figure 1. table 1. 48-lead 14-/16-/18-bit pulsar selection type 100 ksps to 250 ksps 500 ksps to 570 ksps 570 ksps to 1000 ksps >1000 ksps pseudo differential ad7651 ad7660 ad7661 ad7650 ad7652 ad7664 ad7666 ad7653 ad7667 true bipolar ad7610 ad7663 ad7665 ad7951 ad7612 ad7671 true differential ad7675 ad7676 ad7677 ad7621 ad7622 ad7623 18-bit, true differential ad7678 ad7679 ad7674 ad7641 ad7643 multichannel/ simultaneous ad7654 ad7655
ad7951 data sheet rev. a | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ........................................... 12 terminology .................................................................................... 16 theory of operation ...................................................................... 17 overview ...................................................................................... 17 converter operation .................................................................. 17 modes of operation ................................................................... 18 transfer functions...................................................................... 18 typical connecti on diagram ................................................... 19 analog inputs .............................................................................. 20 driver amplifier choice ........................................................... 21 voltage reference input/output .............................................. 21 power supplies ............................................................................ 22 conversion control ................................................................... 23 interfaces.......................................................................................... 24 digital interface .......................................................................... 24 parallel interface ......................................................................... 24 serial interface ............................................................................ 25 master serial interface ............................................................... 25 slave serial interface .................................................................. 27 hardware configuration ........................................................... 29 software configuration ............................................................. 29 microprocessor interfacing ....................................................... 30 application information ................................................................ 31 layout guidelines....................................................................... 31 evaluating performance ............................................................ 31 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history 12/12rev. 0 to rev. a added exposed pad note ................................................................ 8 changes to power sequencing section ........................................ 23 updated outline dimensions ....................................................... 32 changes to ordering guide .......................................................... 32 10/06revision 0: initial version
data sheet ad7951 rev. a | page 3 of 32 specifications avdd = dvdd = 5 v; ovdd = 2.7 v to 5.5 v; vcc = 15 v; vee = ?15 v; v ref = 5 v; all specifications t min to t max , unless otherwise noted. table 2. parameter conditions/comments min typ max unit resolution 14 bits analog input voltage range, v in v in+ ? v in? = 0 v to 5 v ?0.1 +5.1 v v in+ ? v in? = 0 v to 10 v ?0.1 +10.1 v v in+ ? v in? = 5 v ?5.1 +5.1 v v in+ ? v in? = 10 v ?10.1 +10.1 v v in? to agnd ?0.1 +0.1 v analog input cmrr f in = 100 khz 75 db input current v in = 5 v, 10 v @ 1 msps 300 1 a input impedance see the analog inputs section throughput speed complete cycle in warp mode 1 s throughput rate in warp mode 1 1 msps time between conversions in warp mode 1 ms complete cycle in normal mode 1.25 s throughput rate in normal mode 0 800 ksps complete cycle in impulse mode 1.49 s throughput rate in impulse mode 0 670 ksps dc accuracy integral linearity error 2 ?1 0.3 +1 lsb 3 no missing codes 2 14 bits differential linearity error 2 ?1 +1 lsb transition noise 0.55 lsb zero error (unipolar or bipolar) ?15 +15 lsb zero error temperature drift 1 ppm/c full-scale error (unipolar or bipolar) ?20 +20 lsb full-scale error temperature drift 1 ppm/c power supply sensitivity avdd = 5 v 5% 0.8 lsb ac accuracy dynamic range f in = 2 khz, ?60 db 84.5 85.5 db 4 signal-to-noise ratio f in = 2 khz 84.5 85.5 db f in = 20 khz 85.5 db signal-to-(noise + distortion) (sinad) f in = 2 khz 83 85.4 db total harmonic distortion f in = 2 khz ?105 db spurious-free dynamic range f in = 2 khz 102 db C3 db input bandwidth v in = 0 v to 5 v 45 mhz aperture delay 2 ns aperture jitter 5 ps rms transient response full-scale step 500 ns internal reference pdref = pdbuf = low output voltage ref @ 25c 4.965 5.000 5.035 v temperature drift C40c to +85c 3 ppm/c line regulation avdd = 5 v 5% 15 ppm/v long-term drift 1000 hours 50 ppm turn-on settling time c ref = 22 f 10 ms
ad7951 data sheet rev. a | page 4 of 32 parameter conditions/comments min typ max unit reference buffer pdref = high refbufin input voltage range 2.4 2.5 2.6 v external reference pdref = pdbuf = high voltage range ref 4.75 5 avdd + 0.1 v current drain 1 msps throughput 200 a temperature pin voltage output @ 25c 311 mv temperature sensitivity 1 mv/c output resistance 4.33 k digital inputs logic levels v il ?0.3 +0.6 v v ih 2.1 ovdd + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format parallel or serial 14-bit pipeline delay 5 v ol i sink = 500 a 0.4 v v oh i source = C500 a ovdd ? 0.6 v power supplies specified performance avdd 4.75 6 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 v vcc 7 15 15.75 v vee ?15.75 ?15 0 v operating current 7, 8 @ 1 msps throughput avdd with internal reference 20 ma with internal reference disabled 18.5 ma dvdd 7 ma ovdd 0.5 ma vcc vcc = 15 v, with internal reference buffer 4 ma vcc = 15 v 3 ma vee vee = ?15 v 2 ma power dissipation @ 1 msps throughput with internal reference pdref = pdbuf = low 235 260 mw with internal reference disabled pdref = pdbuf = high 215 240 mw in power-down mode 9 pd = high 10 w temperature range 10 specified performance t min to t max ?40 +85 c 1 with v in = 0 v to 5 v or 0 v to 10 v ranges, the input current is typically 100 a. in all input ranges, the input current scales with throughput. see the analog inputs section. 2 linearity is tested using endpoints, not best fit. all linearity is tested with an external 5 v reference. 3 lsb means least significant bit. all specifications in lsb do not include the error contributed by the reference. 4 all specifications in db are referred to a full-scale range input, fsr. tested with an input signal at 0.5 db below full-scale, unless otherwise specified. 5 conversion results are available imme diately after completed conversion. 6 4.75 v or v ref C 0.1 v, whichever is larger. 7 tested in parallel reading mode. 8 with internal reference, pdref = pdbuf = low; with internal reference disabled, pdref = pdbuf = high. with internal reference buffer, pdbuf = low. 9 with all digital inputs forced to ovdd. 10 consult sales for extended temperature range.
data sheet ad7951 rev. a | page 5 of 32 timing specifications avdd = dvdd = 5 v; ovdd = 2.7 v to 5.5 v; vcc = 15 v; vee = ?15 v; v ref = 5 v; all specifications t min to t max , unless otherwise noted. table 3. parameter symbol min typ max unit conversion and reset (see figure 33 and figure 34) convert pulse width t 1 10 ns time between conversions t 2 warp mode/normal mode/impulse mode 1 1/1.25/1.49 s cnvst low to busy high delay t 3 35 ns busy high all modes (except master serial read after convert) t 4 warp mode/normal mode/impulse mode 850/1100/1350 ns aperture delay t 5 2 ns end of conversion to busy low delay t 6 10 ns conversion time t 7 warp mode/normal mode/impulse mode 850/1100/1350 ns acquisition time t 8 warp mode/normal mode/impulse mode 200 ns reset pulse width t 9 10 ns parallel interface modes (see figure 35 and figure 37) cnvst low to data valid delay t 10 warp mode/normal mode/impulse mode 850/1100/1350 ns data valid to busy low delay t 11 20 ns bus access request to data valid t 12 40 ns bus relinquish time t 13 2 15 ns master serial interface modes 2 (see figure 39 and figure 40) cs low to sync valid delay t 14 10 ns cs low to internal sdclk valid delay 2 t 15 10 ns cs low to sdout delay t 16 10 ns cnvst low to sync delay, read during convert t 17 warp mode/normal mode/impulse mode 50/290/530 ns sync asserted to sdclk first edge delay t 18 3 ns internal sdclk period 3 t 19 30 45 ns internal sdclk high 3 t 20 15 ns internal sdclk low 3 t 21 10 ns sdout valid setup time 3 t 22 4 ns sdout valid hold time 3 t 23 5 ns sdclk last edge to sync delay 3 t 24 5 ns cs high to sync high-z t 25 10 ns cs high to internal sdclk high-z t 26 10 ns cs high to sdout high-z t 27 10 ns busy high in master serial read after convert 3 t 28 see table 4 cnvst low to sync delay, read after convert t 29 warp mode/normal mode/impulse mode 710/950/1190 ns sync deasserted to busy low delay t 30 25 ns
ad7951 data sheet rev. a | page 6 of 32 parameter symbol min typ max unit slave serial/serial configuration interface modes 2 (see figure 42, figure 43, and figure 45) external sdclk, scclk setup time t 31 5 ns external sdclk active edge to sdout delay t 32 2 18 ns sdin/scin setup time t 33 5 ns sdin/scin hold time t 34 5 ns external sdclk/scclk period t 35 25 ns external sdclk/scclk high t 36 10 ns external sdclk/scclk low t 37 10 ns 1 in warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time. 2 in serial interface modes, the sdsync, sdsclk, and sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 3 in serial master read during co nvert mode. see table 4 for serial master read after convert mode. table 4. serial clock timings in master read after convert mode divsclk[1] 0 0 1 1 divsclk[0] symbol 0 1 0 1 unit sync to sdclk first edge delay minimum t 18 3 20 20 20 ns internal sdclk period minimum t 19 30 60 120 240 ns internal sdclk period maximum t 19 45 90 180 360 ns internal sdclk high minimum t 20 12 30 60 120 ns internal sdclk low minimum t 21 10 25 55 115 ns sdout valid setup time minimum t 22 4 20 20 20 ns sdout valid hold time minimum t 23 5 8 35 90 ns sdclk last edge to sync delay minimum t 24 5 7 35 90 ns busy high width maximum t 28 warp mode 1.60 2.35 3.75 6.75 s normal mode 1.85 2.60 4.00 7.00 s impulse mode 2.10 2.85 4.25 7.25 s notes 1. in serial interface modes, the sync, sclk, and sdout are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. 1.6ma i ol 500a i oh 1.4v to output pin c l 60pf 0 6396-002 figure 2. load circuit for digital interface timing, sdout, sync, and sclk outputs, c l = 10 pf 0.8v 2v 2v 0.8v 0.8v 2v t delay t delay 06396-003 figure 3. voltage reference levels for timing
data sheet ad7951 rev. a | page 7 of 32 absolute maximum ratings table 5. parameter rating analog inputs/outputs in+ 1 , in? 1 to agnd vee ? 0.3 v to vcc + 0.3 v ref, refbufin, temp, refgnd to agnd avdd + 0.3 v to agnd ? 0.3 v ground voltage differences agnd, dgnd, ognd 0.3 v supply voltages avdd, dvdd, ovdd ?0.3 v to +7 v avdd to dvdd, avdd to ovdd 7 v dvdd to ovdd 7 v vcc to agnd, dgnd C0.3 v to +16.5 v vee to gnd +0.3 v to ?16.5 v digital inputs ?0.3 v to ovdd + 0.3 v pdref, pdbuf 2 20 ma internal power dissipation 3 700 mw internal power dissipation 4 2.5 w junction temperature 125c storage temperature range ?65c to +125c 1 see the analog inputs section. 2 see the voltage reference input section. 3 specification is for the device in free air: 48-lead lqfp; ja = 91c/w, jc = 30c/w. 4 specification is for the device in free air: 48-lead lfcsp; ja = 26c/w. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7951 data sheet rev. a | page 8 of 32 pin configuration and fu nction descriptions 06396-004 pdbuf pdref refbufin temp avdd in+ agnd vee vcc in? refgnd ref d2/ext/int d3/invsync d4/invsclk d5/rdc/sdin ognd ovdd dvdd dgnd d6/sdout d7/sdclk d8/sync d9/rderror agnd avdd agnd byteswap ob/2c ser/par nc nc d0/divsclk[0] d1/divsclk[1] impulse warp bipolar cnvst pd reset cs rd ten busy d13/sccs d12/scclk d11/scin d10/hw/sw 48 47 46 45 44 43 42 41 40 39 38 37 35 34 33 30 31 32 36 29 28 27 25 26 2 3 4 7 6 5 1 8 9 10 12 11 13 14 15 16 17 18 19 20 21 22 23 24 pin 1 ad7951 top view (not to scale) notes 1. nc = no connect. 2. for the lead frame chip scale package (lfcsp), the exposed pad should be connected to vee. this connection is not required to meet the electrical performances. figure 4. pin configuration table 6. pin function descriptions pin no. mnemonic type 1 description 1, 3, 42 agnd p analog power ground pins. ground reference point for all analog i/o. all analog i/o should be referenced to agnd and should be connected to th e analog ground plane of the system. in addition, the agnd, dgnd, and ognd voltages should be at the same potential. 2, 44 avdd p analog power pins. nominally 4.75 v to 5. 25 v and decoupled with 10 f and 100 nf capacitors. 4 byteswap di parallel mode selection (8-bit/14-bit). when high, the lsb is output on d[15: 8] and the msb is output on d[7:0]; when low, the lsb is output on d[7:0] and the msb is output on d[15:8]. 5 ob/2c di 2 straight binary/binary twos complement output. wh en high, the digital output is straight binary. when low, the msb is inverted resulting in a twos complement output from its internal shift register. 6 warp di 2 conversion mode selection. used in conjun ction with the impulse input per the following: conversion mode warp impulse normal low low impulse low high warp high low normal high high see the modes of operation section for a more detailed description. 7 impulse di 2 conversion mode selection. see the warp pin description in the previous row of this table. see the modes of operation section for a more detailed description. 8 ser/par di serial/parallel selection input. when ser/par = low, the parallel mode is selected. when ser/par = high, the serial modes are selected. some bits of the data bus are used as a serial port and the remaining data bits are high impedance outputs. 9, 10 nc do no connect. do not connect.
data sheet ad7951 rev. a | page 9 of 32 pin no. mnemonic type 1 description 11, 12 d[0:1] or di/o in parallel mode, these outputs are used as bit 0 and bit 1 of th e parallel port data output bus. divsclk[0:1] serial data division clock selection. in se rial master read after convert mode (ser/par = high, ext/int = low, rdc/sdin = low) these inputs can be used to slow down the internally generated serial data clock that clocks th e data output. in other serial modes, these pins are high impedance outputs. 13 d2 or di/o in parallel mode, this output is used as bit 2 of the parallel port data output bus. ext/int serial data clock source select. in serial mode, this input is used to select the internally generated (master) or external (slave) serial data clock for the ad7951 output data. when ext/int = low, master mode; the internal serial data clock is selected on sdclk output. when ext/int = high, slave mode; the output data is synchr onized to an external clock signal (gated by cs ) connected to the sdclk input. 14 d3 or di/o in parallel mode, this output is used as bit 3 of the parallel port data output bus. invsync serial data invert sync select. in serial master mode (ser/par = high, ext/int = low). this input is used to select the active state of the sync signal. when invsync = low, sync is active high. when invsync = high, sync is active low. 15 d4 or di/o in parallel mode, this output is used as bit 4 of the parallel port data output bus. invsclk in all serial modes, invert sdclk/scclk sele ct. this input is used to invert both sdclk and scclk. when invsclk = low, the rising edge of sdclk/scclk are used. when invsclk = high, the falling edge of sdclk/scclk are used. 16 d5 or di/o in parallel mode, this output is used as bit 5 of the parallel port data output bus. rdc or serial data read during convert. in serial master mode (ser/par = high, ext/int = low) rdc is used to select the read mode. refer to the master serial interface section. when rdc = low, the current result is read afte r conversion. note the maximum throughput is not attainable in this mode. when rdc = high, the previous conversion result is read during the current conversion. sdin serial data in. in serial slave mode (ser/par = high ext/int = high) sdin can be used as a data input to daisy-chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on sdout with a delay of 16 sdclk periods after the initiation of the read sequence. 17 ognd p input/output interface digital power ground. ground reference point for digital outputs. should be connected to the system digital ground ideally at the same potential as agnd and dgnd. 18 ovdd p input/output interface digital power. nominally at th e same supply as the supply of the host interface 2.5 v, 3 v, or 5 v and decoupled with 10 f and 100 nf capacitors. 19 dvdd p digital power. nominally at 4.75 v to 5.25 v and de coupled with 10 f and 100 nf capacitors. can be supplied from avdd. 20 dgnd p digital power ground. ground reference point for di gital outputs. should be connected to system digital ground ideally at the same potential as agnd and ognd. 21 d6 or do in parallel mode, th is output is used as bit 6 of the parallel port data output bus. sdout serial data output. in all serial modes this pin is used as the se rial data output synchronized to sdclk. conversion results are stored in an on-chip regi ster. the ad7951 provides the conversion result, msb first, from its internal shift register. the data format is determined by the logic level of ob/2c . when ext/int = low (master mode), sdout is valid on both edges of sdclk. when ext/int = high (slave mode): when invsclk = low, sdout is updated on sdclk rising edge. when invsclk = high, sdout is updated on sdclk falling edge. 22 d7 or di/o in parallel mode, this output is used as bit 7 of the parallel port data output bus. sdclk serial data clock. in all serial mode s, this pin is used as the serial data clock input or output, dependent on the logic state of the ext/int pin. the active edge where the data sdout is updated depends on the logic state of the invsclk pin.
ad7951 data sheet rev. a | page 10 of 32 pin no. mnemonic type 1 description 23 d8 or do in parallel mode, th is output is used as bit 8 of the parallel port data output bus. sync serial data frame synchronization. in serial master mode (ser/par = high, ext/int = low), this output is used as a digital output frame synchronizat ion for use with the internal data clock. when a read sequence is initiated and invsync = low, sync is driven high and remains high while the sdout output is valid. when a read sequence is initiated and invsync = high, sync is driven low and remains low while the sdout output is valid. 24 d9 or do in parallel mode, th is output is used as bit 9 of the parallel port data output bus. rderror serial data read error. in serial slave mode (ser/par = high, ext/int = high), this output is used as an incomplete data read error flag. if a data read is started and not completed when the current conversion is complete, the current data is lost and rderror is pulsed high. 25 d10 or di/o in parallel mode, this output is used as bit 10 of the parallel port data output bus. hw/sw serial configuration hardware/software select. in serial mode, this input is used to configure the ad7951 by hardware or software. see the hardware configuration section and software configuration section. when hw/sw = low, the ad7951 is configured through software using the serial configuration register. when hw/sw = high, the ad7951 is configured through dedicated hardware input pins. 26 d11 or di/o in parallel mode, this output is used as bit 11 of the parallel port data output bus. scin serial configuration data input. in seri al software configuration mode (ser/par = high, hw/sw = low) this input is used to serially wr ite in, msb first, the configuration data into the serial configuration register. the data on this input is latched with scclk. see the software configuration section. 27 d12 or di/o in parallel mode, this output is used as bit 12 of the parallel port data output bus. scclk serial configuration clock. in serial software configuration mode (ser/par = high, hw/sw = low) this input is used to clock in the data on scin. the active edge where the data scin is updated depends on the logic state of the invsclk pin. see the software configuration section. 28 d13 or di/o in parallel mode, this output is used as bit 13 of the parallel port data output bus. sccs serial configuration chip select. in serial software configuration mode (ser/par = high, hw/sw = low) this input enables the serial configuration port. see the software configuration section. 29 busy do busy output. transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chi p shift register. the falling edge of busy can be used as a data ready clock signal. note that in master read after convert mode (ser/par = high, ext/int = low, rdc = low), the busy time changes according to table 4. 30 ten di 2 input range select. used in conjunction with bipolar per the following: input range bipolar ten 0 v to 5 v low low 0 v to 10 v low high 5 v high low 10 v high high 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the external clock in slave se rial mode (not used for serial programmable port). 33 reset di reset input. when high, reset the ad7951. current conversion, if any, is aborted. the falling edge of reset resets the data outputs to all zeros (with ob/2c = high) and clears the configuration register. see the digital interface section. if not used, this pin can be tied to ognd. 34 pd di 2 power-down input. when pd = high, powers down the adc. power consumption is reduced and conversions are inhibited after the current one is completed. the digital interface remains active during power-down. 35 cnvst di conversion start. a falling edge on cnvst puts the internal sample-and-hold into the hold state and initiates a conversion. 36 bipolar di 2 input range select. see description for pin 30.
data sheet ad7951 rev. a | page 11 of 32 pin no. mnemonic type 1 description 37 ref ai/o reference input/output. when pdref/pdbuf = low, the internal reference and buffer are enabled, producing 5 v on this pin. when pdref/pdbuf = high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to avdd volts. decoupling with at least a 22 f is required with or without the internal reference and buffer. see the reference decoupling section. 38 refgnd ai reference input analog grou nd. connected to analog ground plane. 39 in? ai analog input ground sense. should be connected to the analog ground plane or to a remote sense ground. 40 vcc p high voltage positive supply. normally +7 v to +15 v. 41 vee p high voltage negative supply. normally 0 v to ?15 v (0 v in unipolar ranges). 43 in+ ai analog input. referenced to in?. 45 temp ao temperature sensor analog output. enabled wh en the internal reference is turned on (pdref = pdbuf = low). see the temperature sensor section. 46 refbufin ai reference buffer input. when using an external reference with the internal reference buffer (pdbuf = low, pdref = high), applying 2.5 v on this pin produces 5 v on the ref pin. see the voltage reference input section. 47 pdref di internal reference power-down input. when low, the internal reference is enabled. when high, the internal reference is powered down, and an external reference must be used. 48 pdbuf di internal reference buffer power-down input. when low, the buffer is enabled (must be low when using internal reference). when high, the buffer is powered-down. 49 epad 3 nc exposed pad. the exposed pad is not connected internally. it is recommended that the pad be soldered to vee. 1 ai = analog input; ai/o = bidirectional analog; ao = analog output; di = digital input; di/o = bidirectional digital; do = dig ital output; p = power. 2 in serial configura tion mode (ser/ par = high, hw/ sw = low), this input is programmed with the serial configuration regist er and this pin is a dont care. see the hardware configuration section and software configuration section. 3 lfcsp_vq package only.
ad7951 data sheet rev. a | page 12 of 32 typical performance characteristics avdd = dvdd = 5 v; ovdd = 5 v; vcc = 15 v; vee = ?15 v; v ref = 5 v; t a = 25c. ?1.0 ?0.5 0 0.5 1.0 0 4096 8192 12288 16384 code inl (lsb) positive inl = +0.15 negative inl = ?0.15 06396-005 figure 5. integral nonlinearity vs. code 0 50 100 150 200 250 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 negative inl positive inl inl distribution (lsb) number of units 06396-006 figure 6. integral nonlinearity distribution (239 devices) 0 50000 100000 150000 200000 250000 300000 1fff 2000 2001 2002 2003 code in hex counts 00 261120 00 0 6396-007 figure 7. histogram of 261,120 conversions of a dc input at the code center ?1.0 ?0.5 0 0.5 1.0 0 4096 8192 12288 16384 code dnl (lsb) positive dnl = +0.27 negative dnl = ?0.27 06396-008 figure 8. differential nonlinearity vs. code 0 20 40 60 80 100 120 140 160 180 200 number of units ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 negative dnl positive dnl dnl distribution (lsb) 06396-009 figure 9. differential nonlineari ty distribution (239 devices) 0 20000 40000 60000 80000 100000 120000 140000 8192 8193 8194 8195 8196 8197 00 132052 0 129068 0 code in hex counts 0 6396-010 figure 10. histogram of 261,120 conversions of a dc input at the code transition
data sheet ad7951 rev. a | page 13 of 32 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 100 200 400 300 500 frequency (khz) amplitude (db of full scale) f s = 1000ksps f in = 19.94khz snr = 85.4db thd = ?107db sfdr = 116db sinad = 85.4db 0 6396-011 figure 11. fft 20 khz 78 80 82 84 86 88 110100 13.5 13.7 13.9 14.1 14.3 14.5 enob (bits) snr sinad enob frequency (khz) snr, sinad (db) 06396-012 figure 12. snr, sinad, and enob vs. frequency 84.0 84.5 85.0 85.5 86.0 ?55 ?35 ?15 5 25 45 65 85 105 125 0v to 5v 0v to 10v 5v 10v temperature (c) snr (db) 06396-013 figure 13. snr vs. temperature 85.0 85.5 86.0 86.5 ?60 ?50 ?40 ?30 ?20 ?10 0 06396-014 input level (db) snr, sinad referred to full scale (db) snr sinad figure 14. snr and sinad vs. input level (referred to full scale) ?130 ?120 ?110 ?100 ?90 ?80 ? 70 1 10 100 60 70 80 90 100 110 120 sfdr (db) sfdr thd second harmonic thd, harmonics (db) frequency (khz) third harmonic 06396-015 figure 15. thd, harmonics, and sfdr vs. frequency 84.0 84.5 85.0 85.5 86.0 temperature (c) sinad (db) ?55 ?35 ?15 5 25 45 65 85 105 125 0v to 5v 0v to 10v 5v 10v 06396-016 figure 16. sinad vs. temperature
ad7951 data sheet rev. a | page 14 of 32 ?120 ?116 ?112 ?108 ?104 ?100 ? 96 temperature (c) thd (db) ?55 ?35 ?15 5 25 45 65 85 105 125 0v to 5v 0v to 10v 5v 10v 06396-017 figure 17. thd vs. temperature 1.5 ?1.5 ?55 125 zero error, full scale error (lsb) temperature (c) 1.0 0 0.5 ?0.5 ?1.0 25 65 85 105 ?35 ?15 5 45 zero error positive fs error negative fs error 06396-018 figure 18. zero error, positive and negative full scale vs. temperature 60 0 08 reference drift (ppm/c) number of units 50 40 30 20 10 1234567 06396-019 figure 19. reference voltage temperature coefficient distribution (247 devices) 106 108 110 112 114 116 118 120 122 124 temperature (c) sfdr (db) ?55 ?35 ?15 5 25 45 65 85 105 125 0v to 5v 0v to 10v 5v 10v 06396-020 figure 20. sfdr vs. temperature (excludes harmonics) 5.008 4.996 ?55 125 vref (v) temperature (c) 5.006 5.002 5.004 5.000 4.998 25 65 85 105 ?35 ?15 5 45 06396-021 figure 21. typical reference voltage output vs. temperature (3 devices) 100000 0.001 1000000 operating currents (a) sampling rate (sps) 06396-022 100 10 10 100 1000 10000 100000 1000 1 0.1 0.01 10000 pdref = pdbuf = high vcc +15v vee ?15v all modes avdd, warp/normal ovdd, all modes dvdd, all modes avdd, impulse figure 22. operating currents vs. sample rate
data sheet ad7951 rev. a | page 15 of 32 0 100 200 300 400 500 600 700 06396-023 temperature (c) power?down operating currents (na) ?55 ?35 ?15 5 25 45 65 85 105 pd = pdbuf = pdref = high vee = ?15v vcc = +15v dvdd ovdd avdd figure 23. power-down operating currents vs. temperature 0 5 10 15 20 25 30 35 40 45 50 0 50 100 150 200 c l (pf) t 12 delay (ns) ovdd = 2.7v @ 25c ovdd = 2.7v @ 85c ovdd = 5v @ 85c ovdd = 5v @ 25c 0 6396-024 figure 24. typical delay vs. load capacitance c l
ad7951 data sheet rev. a | page 16 of 32 terminology least significant bit (lsb) the least significant bit, or lsb, is the smallest increment that can be represented by a converter. for an analog-to-digital converter with n bits of resolution, the lsb expressed in volts is n pinp v lsb 2 (max) (v) ? ? integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full-scale through positive full- scale. the point used as negative full-scale occurs a ? lsb before the first code transition. positive full-scale is defined as a level 1? lsbs beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. bipolar zero error the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. unipolar offset error the first transition should occur at a level ? lsb above analog ground. the unipolar offset error is the deviation of the actual transition from that point. full-scale error the last transition (from 11110 to 11111) should occur for an analog voltage 1? lsb below the nominal full-scale. the full-scale error is the deviation in lsb (or % of full-scale range) of the actual level of the last transition from the ideal level and includes the effect of the offset error. closely related is the gain error (also in lsb or % of full-scale range), which does not include the effects of the offset error. dynamic range dynamic range is the ratio of the rms value of the full-scale to the rms noise measured for an input typically at ?60 db. the value for dynamic range is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. signal-to-(noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. spurious-free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad and is expressed in bits by enob = [( sinad db ? 1.76)/6.02] aperture delay aperture delay is a measure of the acquisition performance measured from the falling edge of the cnvst input to when the input signal is held for a conversion. transient resp onse the time required for the ad7951 to achieve its rated accuracy after a full-scale step function is applied to its input. reference voltage temperature coefficient reference voltage temperature coefficient is derived from the typical shift of output voltage at 25c on a sample of parts at the maximum and minimum reference output voltage (v ref ) measured at t min , t(25c), and t max . it is expressed in ppm/c as 6 10 )C()c25( ) C) )cppm/( ? ?? ?? min max ref ref ref ref tt v min(vmax(v tcv where: v ref ( max ) = maximum v ref at t min , t(25c), or t max . v ref ( min ) = minimum v ref at t min , t(25c), or t max . v ref (25 c ) = v ref at 25c. t max = +85c. t min = C40c.
data sheet ad7951 rev. a | page 17 of 32 theory of operation sw a sw b in+ ref refgnd lsb msb 8,192c in? 4,096c 4c 2c c c 16,384c control logic switches control busy output code cnvst comp 06396-025 figure 25. adc simplified schematic overview the ad7951 is a very fast, low power, precise, 14-bit analog-to- digital converter (adc) using successive approximation capacitive digital-to-analog (cdac) converter architecture. the ad7951 can be configured at any time for one of four input ranges and conversion mode with inputs in parallel and serial hardware modes or by a dedicated write only, spi-compatible interface via a configuration register in serial software mode. the ad7951 uses analog devices patented i cmos high voltage process to accommodate 0 to 5 v, 0 to 10 v, 5 v, and 10 v input ranges without the use of conventional thin films. only one acquisition cycle, t 8 , is required for the inputs to latch to the correct configuration. resetting or power cycling is not required for reconfiguring the adc. the ad7951 features different modes to optimize performance according to the applications. it is capable of converting 1,000,000 samples per second (1 msps) in warp mode, 800 ksps in normal mode, and 670 ksps in impulse mode. the ad7951 provides the user with an on-chip track-and-hold, successive approximation adc that does not exhibit any pipe- line or latency, making it ideal for multiple, multiplexed channel applications. for unipolar input ranges, the ad7951 typically requires three supplies; vcc, avdd (which can supply dvdd), and ovdd which can be interfaced to either 5 v, 3.3 v, or 2.5 v digital logic. for bipolar input ranges, the ad7951 requires the use of the additional vee supply. the device is housed in pb-free, 48-lead lqfp or tiny lfcsp 7 mm 7 mm packages that combine space savings with flexibility. in addition, the ad7951 can be configured as either a parallel or a serial spi-compatible interface. converter operation the ad7951 is a successive approximation adc based on a charge redistribution dac. figure 25 shows the simplified schematic of the adc. the cdac consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparators input are connected to agnd via sw+ and sw?. all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on in+ and in? inputs. a conversion phase is initiated once the acquisition phase is complete and the cnvst input goes low. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the refgnd input. therefore, the differential voltage between the inputs (in+ and in?) captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between refgnd and ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4 through v ref / 16,384). the control logic toggles these switches, starting with the msb first, in order to bring the comparator back into a balanced condition. after the completion of this process, the control logic generates the adc output code and brings the busy output low.
ad7951 data sheet rev. a | page 18 of 32 modes of operation the ad7951 features three modes of operation: warp, normal, and impulse. each of these modes is more suitable to specific applications. the mode is configured with the input pins, warp and impulse, or via the configuration register. see table 6 for the pin details and the hardware configuration section and software configuration section for programming the mode selection with either pins or configuration register. note that when using the configuration register, the warp and impulse inputs are dont cares and should be tied to either high or low. warp mode setting warp = high and impulse = low allows the fastest conversion rate up to 1 msps. however, in this mode, the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. if the time between two consecutive conversions is longer than 1 ms (after power-up), the first conversion result should be ignored since in warp mode, the adc performs a background calibration during the sar conversion process. this calibration can drift if the time between conversions exceeds 1 ms thus causing the first conversion to appear offset. this mode makes the ad7951 ideal for applications where both high accuracy and fast sample rate are required. normal mode setting warp = impulse = low or warp = impulse = high allows the fastest mode (800 ksps) without any limitation on time between conversions. th is mode makes the ad7951 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. impulse mode setting warp = low and impulse = high uses the lowest power dissipation mode and allows power saving between conversions. the maximum throughput in this mode is 670 ksps and in this mode, the adc powers down circuits after conversion making the ad7951 ideal for battery-powered applications. transfer functions using the ob/ 2c digital input or via the configuration register, the ad7951 offers two output codings: straight binary and twos complement. see figure 26 and table 7 for the ideal transfer characteristic and digital output codes for the different analog input ranges, v in . note that when using the configuration register, the ob/ 2c input is a dont care and should be tied to either high or low. 000...000 000...001 000...010 111...101 111...110 111...111 adc code (straight binary) analog input +fsr ? 1.5 lsb +fsr ?1lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 06396-026 figure 26. adc ideal transfer function table 7. output codes and ideal input voltages v ref = 5 v digital output code description v in = 5 v v in = 10 v v in = 5 v v in = 10 v straight binary twos complement fsr ? 1 lsb 4.999695 v 9.999389 v +4.999389 v +9.998779 v 0x3fff 1 0x1fff 1 fsr ? 2 lsb 4.999390 v 9.998779 v +4.998779 v +9.997558 v 0x3ffe 0x1ffe midscale + 1 lsb 2.500305 v 5.000610 v +610.4 v +1.221 mv 0x2001 0x0001 midscale 2.5 v 5.000000 v 0 v 0 v 0x2000 0x0000 midscale ? 1 lsb 2.499695 v 4.999389 v ?610.4 v ?1.221 mv 0x1fff 0x3fff ?fsr + 1 lsb 305.2 v 610.4 v ?4.999389 v ?9.998779 v 0x0001 0x2001 ?fsr 0 v 0 v ?5 v ?10 v 0x0000 2 0x2000 2 1 this is also the code fo r overrange analog input (v in+ ? v in? above v ref ? v refgnd ). 2 this is also the code fo r overrange analog input (v in+ ? v in? below v ref ? v refgnd ).
data sheet ad7951 rev. a | page 19 of 32 typical connection diagram figure 27 shows a typical connection diagram for the ad7951 using the internal reference, serial data and serial configuration interfaces. different circuitry from that shown in figure 27 is optional and is discussed in the following sections. rd cs 100nf 100nf avdd 10f 100nf agnd dgnd dvdd ovdd ognd cnvst busy sdout sdclk reset pd refbufin d clock ad7951 microconverter/ microprocessor/ dsp digital interface supply (2.5v, 3.3v, or 5v) analog supply (5v) ovdd digital supply (5v) in+ in? note 5 analog input+ c c 2.7nf u1 note 1 ser/par ob/2c refgnd ref pdbuf pdref 100nf note 3 note 4 note 3 note 7 10f 10f c ref 22f notes 1. see analog input section. analog input(?) is referenced to agnd 0.1v. 2. the ad8021 is recommended. see driver amplifier choice section. 3. the configuration shown is using the internal reference. see voltage reference input section. 4. a 22f ceramic capacitor (x5r, 1206 size) is recommended (for example, panasonic ecj4yb1a226m). see voltage reference input section. 5. option, see power supply section. 6. the vcc and vee supplies should be vcc = [vin(max) +2v] and vee = [vin(min) ?2v] for bipolar input ranges. for unipolar input ranges, vee can be 0v. see power supply section. 7. optional low jitter cnvst, see conversion control section. analog input? note 2 vcc vee 10f 100nf +7v to +15.75v supply 10f 100nf ?7v to ?15.75v supply note 6 hw/sw sccs scclk scin bipolar ten serial port 1 serial port 2 warp impulse 06396-027 50 ? 15 ? 10? figure 27. typical connection diagram shown with serial interface and serial programmable port
ad7951 data sheet rev. a | page 20 of 32 analog inputs input range selection in parallel mode and serial hardware mode, the input range is selected by using the bipolar (bipolar) and ten (10 volt range) inputs. see table 6 for pin details and the hardware configuration section and software configuration section for programming the mode selection with either pins or configuration register. note that when using the configuration register, the bipolar and ten inputs are dont cares and should be tied to either high or low. input structure figure 28 shows an equivalent circuit for the input structure of the ad7951. d1 r in c in d2 in+ or in? vee vcc c pin agnd d3 d4 avdd 0 v to 5v range only 0 6396-028 figure 28. ad7951 simplified analog input the four diodes, d1 to d4, provide esd protection for the analog inputs, in+ and in?. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v, because this causes the diodes to become forward-biased and to start conducting current. these diodes can handle a forward- biased current of 120 ma maximum. for instance, these conditions could eventually occur when the input buffers u1 supplies are different from avdd, vcc, and vee. in such a case, an input buffer with a short-circuit current limitation can be used to protect the part although most op amps short circuit current is <100 ma. note that d3 and d4 are only used in the 0 v to 5 v range to allow for additional protection in applications that are switching from the higher voltage ranges. this analog input structure allows the sampling of the differential signal between in+ and in?. by using this differential input, small signals common to both inputs are rejected as shown in figure 29, which represents the typical cmrr over frequency. for instance, by using in? to sense a remote signal ground, ground potential differences between the sensor and the local adc ground are eliminated. 100 0 1 10000 frequency (khz) cmrr (db) 90 80 70 60 50 40 30 20 10 10 100 1000 06396-029 figure 29. analog input cmrr vs. frequency during the acquisition phase for ac signals, the impedance of the analog inputs, in+ and in?, can be modeled as a parallel combination of capacitor c pin and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 70 and is a lumped component comprised of serial resistors and the on resistance of the switches. c in is primarily the adc sampling capacitor and depending on the input range selected is typically 48 pf in the 0 v to 5 v range, typically 24 pf in the 0 v to 10 v and 5 v ranges and typically 12 pf in the 10 v range. during the conversion phase, when the switches are opened, the input impedance is limited to c pin . since the input impedance of the ad7951 is very high, it can be directly driven by a low impedance source without gain error. to further improve the noise filtering achieved by the ad7951 analog input circuit, an external, one-pole rc filter between the amplifiers outputs and the adc analog inputs can be used, as shown in figure 27. however, large source impedances signifi- cantly affect the ac performance, especially total harmonic distortion (thd). the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency.
data sheet ad7951 rev. a | page 21 of 32 driver amplifier choice although the ad7951 is easy to drive, the driver amplifier must meet the following requirements: ? for multichannel, multiplexed applications, the driver amplifier and the ad7951 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 14-bit level (0.006%). for the amplifier, settling at 0.1% to 0.01% is more commonly specified. this differs significantly from the settling time at a 14-bit level and should be verified prior to driver selection. the ad8021 op amp com- bines ultralow noise and high gain bandwidth and meets this settling time requirement even when used with gains of up to 13. ? the noise generated by the driver amplifier needs to be kept as low as possible to pr eserve the snr and transition noise performance of the ad7 951. the noise coming from the driver is filtered by the ex ternal one-pole low-pass filter as shown in figure 27. the snr degradation due to the amplifier is ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 3 2 2 log20 n db nadc nadc loss nef v v snr where: v nadc is the noise of the adc, which is: 20 10 22 snr inp-p nadc v v ? f C3db is the cutoff frequency of the input filter (3.9 mhz). n is the noise factor of the amplifier (+1 in buffer configuration). e n is the equivalent input voltage noise density of the op amp, in nv/hz. ? the driver needs to have a thd performance suitable to that of the ad7951. figure 15 shows the thd vs. frequency that the driver should exceed. the ad8021 meets these requirements and is appropriate for almost all applications. the ad8021 needs a 10 pf external compensation capacitor that should have good linearity as an npo ceramic or mica type. moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. the ad8022 can also be used when a dual version is needed and a gain of 1 is present. the ad829 is an alternative in applica- tions where high frequency (above 100 khz) performance is not required. in applications with a gain of 1, an 82 pf compensation capacitor is required. the ad8610 is an option when low bias current is needed in low frequency applications. since the ad7951 uses a large geometry, high voltage input switch, the best linearity performance is obtained when using the amplifier at its maximum full power bandwidth. gaining the amplifier to make use of the more dynamic range of the adc results in increased linearity errors. for applications requiring more resolution, the use of an additional amplifier with gain should precede a unity follower driving the ad7951. see table 8 for a list of recommended op amps. table 8. recommended driver amplifiers amplifier typical application ada4841-x 12 v supply, very low noise, low distortion, low power, low frequency ad829 15 v supplies, very low noise, low frequency ad8021 12 v supplies, very low noise, high frequency ad8022 12 v supplies, very low noise, high frequency, dual ad8610/ ad8620 13 v supplies, low bias current, low frequency, single/dual voltage reference input/output the ad7951 allows the choice of either a very low temperature drift internal voltage reference, an external reference, or an external buffered reference. the internal reference of the ad7951 provides excellent perform- ance and can be used in almost all applications. however, the linearity performance is guaranteed only with an external reference.
ad7951 data sheet rev. a | page 22 of 32 internal reference (ref = 5 v) (pdref = low, pdbuf = low) to use the internal reference, the pdref and pdbuf inputs must be low. this enables the on-chip band gap reference, buffer, and temp sensor resulting in a 5.00 v reference on the ref pin. the internal reference is temperature-compensated to 5.000 v 35 mv. the reference is trimmed to provide a typical drift of 3 ppm/c. this typical drift characteristic is shown in figure 19. external 2.5 v reference and internal buffer (ref = 5 v) (pdref = high, pdbuf = low) to use an external reference with the internal buffer, pdref should be high and pdbuf should be low. this powers down the internal reference and allows the 2.5 v reference to be applied to refbufin producing 5 v on the ref pin. the internal reference buffer is useful in multiconverter applications because a buffer is typically required in these applications. external 5 v reference (pdref = high, pdbuf = high) to use an external reference directly on the ref pin, pdref and pdbuf should both be high. pdref and pdbuf power down the internal reference and the internal reference buffer, respectively. for improved drift performance, an external reference such as the adr445 or adr435 is recommended. reference decoupling whether using an internal or external reference, the ad7951 voltage reference input (ref) has a dynamic input impedance; therefore, it should be driven by a low impedance source with efficient decoupling between the ref and refgnd inputs. this decoupling depends on the choice of the voltage reference, but usually consists of a low esr capacitor connected to ref and refgnd with minimum parasitic inductance. a 22 f (x5r, 1206 size) ceramic chip capacitor (or 47 f tantalum capacitor) is appropriate when using either the internal reference or the adr445/adr435 external reference. the placement of the reference decoupling is also important to the performance of the ad7951. the decoupling capacitor should be mounted on the same side as the adc, right at the ref pin with a thick pcb trace. the refgnd should also connect to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias. for applications that use multiple ad7951 or other pulsar devices, it is more effective to use the internal reference buffer to buffer the external 2.5 v reference voltage. the voltage reference temperature coefficient (tc) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the tc. for instance, a 15 ppm/c tc of the reference changes full-scale by 1 lsb/c. temperature sensor when the internal reference is enabled (pdref = pdbuf = low), the on-chip temperature sensor output (temp) is enabled and can be use to measure the temperature of the ad7951. to improve the calibration accuracy over the temperature range, the output of the temp pin is applied to one of the inputs of the analog switch (such as adg779 ), and the adc itself is used to measure its own temperature. this configuration is shown in figure 30. adg779 c c analog input ad7951 in+ temperature sensor temp 06396-030 figure 30. use of the temperature sensor power supplies the ad7951 uses five sets of power supply pins: ? avdd: analog 5 v core supply ? vcc: analog high voltage positive supply ? vee: high voltage negative supply ? dvdd: digital 5 v core supply ? ovdd: digital input/output interface supply core supplies the avdd and dvdd supply the ad7951 analog and digital cores respectively. sufficient decoupling of these supplies is required consisting of at least a 10 f capacitor and 100 nf on each supply. the 100 nf capacitors should be placed as close as possible to the ad7951. to reduce the number of supplies needed, the dvdd can be supplied through a simple rc filter from the analog supply, as shown in figure 27. high voltage supplies the high voltage bipolar supplies, vcc and vee are required and must be at least 2 v larger than the maximum input, v in . for example, if using the bipolar 10 v range, the supplies should be 12 v minimum. sufficient decoupling of these supplies is also required consisting of at least a 10 f capacitor and 100 nf on each supply. for unipolar operation, the vee supply can be grounded with some slight thd performance degradation. digital output supply the ovdd supplies the digital outputs and allows direct interface with any logic working between 2.3 v and 5.25 v. ovdd should be set to the same level as the system interface. sufficient decoupling is required, consisting of at least a 10 f capacitor and 100 nf with the 100 nf placed as close as possible to the ad7951.
data sheet ad7951 rev. a | page 23 of 32 power sequencing the ad7951 requires sequencing of the avdd and dvdd supplies. avdd should come up prior to or simultaneously with dvdd. this can be achieved using the configuration in figure 27 or sequencing the supplies in that manner. the other supplies can be sequenced as desired as long as absolute maximum ratings are observed. the ad7951 is very insensitive to power supply variations on avdd over a wide frequency range, as shown in figure 31. 80 75 1 10000 frequency (khz) psrr (db) 10 100 1000 70 65 60 55 50 45 40 35 30 ext ref int ref 0 6396-031 figure 31. avdd psrr vs. frequency power dissipation vs. throughput in impulse mode, the ad7951 automatically reduces its power consumption at the end of each conversion phase. during the acquisition phase, the operating currents are very low, which allows a significant power savings when the conversion rate is reduced (see figure 32). this feature makes the ad7951 ideal for very low power, battery-operated applications. it should be noted that the digital interface remains active even during the acquisition phase. to reduce the operating digital supply currents even further, drive the digital inputs close to the power rails (that is, ovdd and ognd). 1000 1 10 1000000 power dissipation (mw) 06396-032 100 10 100 1000 10000 100000 pdref = pdbuf = high warp mode power impulse mode power figure 32. power dissipa tion vs. sample rate power down setting pd = high powers down the ad7951, thus reducing supply currents to their minimums as shown in figure 23. when the adc is in power down, the current conversion (if any) is completed and the digital bus remains active. to further reduce the digital supply currents, drive the inputs to ovdd or ognd. power down can also be programmed with the configuration register. see the software configuration section for details. note that when using the configuration register, the pd input is a dont care and should be tied to either high or low. conversion control the ad7951 is controlled by the cnvst input. a falling edge on cnvst is all that is necessary to initiate a conversion. detailed timing diagrams of the conversion process are shown in figure 33. once initiated, it cannot be restarted or aborted, even by the power-down input, pd, until the conversion is complete. the cnvst signal operates independently of cs and rd signals. busy mode convert acquire acquire convert cnvst t 1 t 2 t 4 t 3 t 5 t 6 t 7 t 8 0 6396-033 figure 33. basic conversion timing although cnvst is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot, undershoot, or ringing. the cnvst trace should be shielded with ground and a low value (such as 50 ) serial resistor termination should be added close to the output of the component that drives this line. for applications where snr is critical, the cnvst signal should have very low jitter. this can be achieved by using a dedicated oscillator for cnvst generation, or by clocking cnvst with a high frequency, low jitter clock, as shown in figure 27.
ad7951 data sheet rev. a | page 24 of 32 interfaces digital interface the ad7951 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. the serial interface is multiplexed on the parallel data bus. the ad7951 digital interface also accommodates 2.5 v, 3.3 v, or 5 v logic. in most applications, the ovdd supply pin is connected to the host system interface 2.5 v to 5.25 v digital supply. finally, by using the ob/ 2c input pin, both twos complement or straight binary coding can be used. two signals, cs and rd , control the interface. when at least one of these signals is high, the interface outputs are in high impedance. usually, cs allows the selection of each ad7951 in multicircuit applications and is held low in a single ad7951 design. rd is generally used to enable the conversion result on the data bus. reset the reset input is used to reset the ad7951. a rising edge on reset aborts the current conversion (if any) and tristates the data bus. the falling edge of reset resets the ad7951 and clears the data bus and configuration register. see figure 34 for the reset timing details. t 9 t 8 reset data bus busy cnvst 0 6396-034 figure 34. reset timing parallel interface the ad7951 is configured to use the parallel interface when ser/ par is held low. master parallel interface data can be continuously read by tying cs and rd low, thus requiring minimal microprocessor connections. however, in this mode, the data bus is always driven and cannot be used in shared bus applications (unless the device is held in reset). figure 35 details the timing for this mode. t 1 busy data bus previous conversion data new data cnvst cs = rd = 0 t 10 t 4 t 11 t 3 06396-035 figure 35. master parallel data timing for reading (continuous read) slave parallel interface in slave parallel reading mode, the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in figure 36 and figure 37, respectively. when the data is read during the conver- sion, it is recommended that it is read only during the first half of the conversion phase. this avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. current conversion t 13 t 12 busy data bus rd cs 06396-036 figure 36. slave parallel data timing for reading (read after convert) previous conversion t 13 t 12 t 3 busy data bus cnvst, rd cs = 0 t 4 t 1 06396-037 figure 37. slave parallel data timing for reading (read during convert)
data sheet ad7951 rev. a | page 25 of 32 8-bit interface (master or slave) the byteswap pin allows a glueless interface to an 8-bit bus. as shown in figure 38, when byteswap is low, the lsb byte is output on d[7:0] and the msb is output on d[13:8]. when byteswap is high, the lsb and msb bytes are swapped; the lsb is output on d[13:8] and the msb is output on d[7:0]. by connecting byteswap to an address line, the 14-bit data can be read in two bytes on either d[13:8] or d[7:0]. this interface can be used in both master and slave parallel reading modes. cs rd byteswap pins d[13:8] pins d[7:0] hi-z hi-z high byte low byte low byte high byte hi-z hi-z t 12 t 12 t 13 06396-038 figure 38. 8-bit and 14-bit parallel interface serial interface the ad7951 has a serial interface (spi-compatible) multiplexed on the data pins d[13:0]. the ad7951 is configured to use the serial interface when ser/ par is held high. data interface the ad7951 outputs 14 bits of data, msb first, on the sdout pin. this data is synchronized with the 14 clock pulses provided on the sdclk pin. the output data is valid on both the rising and falling edge of the data clock. serial configuration interface the ad7951 can be configured through the serial configuration register only in serial mode, as the serial configuration pins are also multiplexed on the data pins d[13:10]. refer to the hardware configuration section and software configuration section for more information. master serial interface the pins multiplexed on d[8:0] and used for master serial interface are: divsclk[0], divsclk[1], ext/ int , invsync, invsclk, rdc, sdout, sdclk and sync. internal clock (ser/ par = high, ext/ int = low) the ad7951 is configured to generate and provide the serial data clock, sdclk, when the ext/ int pin is held low. the ad7951 also generates a sync signal to indicate to the host when the serial data is valid. the sdclk, and the sync signals can be inverted, if desired using the invsclk and invsync inputs, respectively. depending on the input, rdc, the data can be read during the following conversion or after each conversion. figure 39 and figure 40 show detailed timing diagrams of these two modes. read during convert (rdc = high) setting rdc = high, allows the master read (previous conversion result) during conversion mode. usually, because the ad7951 is used with a fast throughput, this mode is the most recommended serial mode. in this mode, the serial clock and data toggle at appropriate instances, minimizing potential feedthrough between digital activity and critical conversion decisions. in this mode, the sdclk period changes since the lsbs require more time to settle and the sdclk is derived from the sar conversion cycle. in this mode, the ad7951 generates a discontinuous sdclk of two different periods and the host should use an spi interface. read after convert (rdc = low, divsclk[1:0] = [0 to 3]) setting rdc = low allows the read after conversion mode. unlike the other serial modes, the busy signal returns low after the 14 data bits are pulsed out and not at the end of the conversion phase, resulting in a longer busy width (refer to table 4 for busy timing specifications). the divsclk[1:0] inputs control the sdclk period and sdout data rate. as a result, the maximum throughput cannot be achieved in this mode. in this mode, the ad7951 also generates a discontinuous sdclk; however, a fixed period and hosts supporting both spi and serial ports can also be used.
ad7951 data sheet rev. a | page 26 of 32 busy sync sdclk sdout 123 121314 d13 d12 d2 d1 d0 x rdc/sdin = 0 invsclk = invsync = 0 cnvst cs, rd ext/int = 0 t 23 t 22 t 16 t 15 t 14 t 29 t 19 t 21 t 20 t 18 t 28 t 30 t 24 t 25 t 26 t 27 t 3 06396-039 figure 39. master serial data timing for reading (read after convert) ext/int = 0 rdc/sdin = 1 invsclk = invsync = 0 d13 d12 d2 d1 d0 x 123 121314 busy sync sdclk sdout cnvst cs, rd t 23 t 18 t 15 t 14 t 17 t 3 t 22 t 16 t 1 t 25 t 26 t 24 t 27 t 19 t 20 t 21 06396-040 figure 40. master serial data timing for reading (read previous conversion during convert)
data sheet ad7951 rev. a | page 27 of 32 slave serial interface the pins multiplexed on d[19:2] used for slave serial interface are: ext/ int , invsclk, sdin, sdout, sdclk and rderror. external clock (ser/ par = high, ext/ int = high) setting the ext/ int = high allows the ad7951 to accept an externally supplied serial data clock on the sdclk pin. in this mode, several methods can be used to read the data. the external serial clock is gated by cs . when cs and rd are both low, the data can be read after each conversion or during the following conversion. a clock can be either normally high or normally low when inactive. for detailed timing diagrams, see figure 42 and figure 43. while the ad7951 is performing a bit decision, it is important that voltage transients be avoided on digital input/output pins, or degradation of the conversion result may occur. this is particularly important during the last 450 ns of the conversion phase because the ad7951 provides error correction circuitry that can correct for an improper bit decision made during the first part of the conversion phase. for this reason, it is recom- mended that any external clock provided is a discontinuous clock that transitions only when busy is low or, more importantly, that it does not transition during the last 450 ns of busy high. external discontinuous clock data read after conversion though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. figure 42 shows the detailed timing diagrams for this method. after a conversion is complete, indicated by busy returning low, the conversion result can be read while both cs and rd are low. data is shifted out msb first with 14 clock pulses and, depending on the sdclk frequency, can be valid on the falling and rising edges of the clock. one advantage of this method is that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. another advantage is the ability to read the data at any speed up to 40 mhz, which accommodates both the slow digital host interface and the fastest serial reading. daisy-chain feature also in the read after convert mode, the ad7951 provides a daisy-chain feature for cascading multiple converters together using the serial data input pin, sdin. this feature is useful for reducing component count and wiring connections when desired, for instance, in isolated multiconverter applications. see figure 42 for the timing details. an example of the concatenation of two devices is shown in figure 41. simultaneous sampling is possible by using a common cnvst signal. note that the sdin input is latched on the opposite edge of sdclk used to shift out the data on sdout (sdclk falling edge when invsclk = low). therefore, the msb of the upstream converter follows the lsb of the downstream converter on the next sdclk cycle. in this mode, the 40 mhz sdclk rate cannot be used since the sdin to sdclk setup time, t 33 , is less than the minimum time specified. (sdclk to sdout delay, t 32 , is the same for all converters when simultaneously sampled). for proper operation, the sdclk edge for latching sdin (or ? period of sdclk) needs to be: 3332 sdclk tt t ? ? 2/1 or the max sdclk frequency needs to be: )(2 1 3332 sdclk tt f ? ? if not using the daisy-chain feature, the sdin input should always be tied either high or low. sclk sdout rdc/sdin ad7951 #1 (downstream) ad7951 #2 (upstream) busy out busy busy data out sclk rdc/sdin sdout sclk in cnvst in cnvst cs cnvst cs cs in 0 6396-041 figure 41. two ad7951 devices in a daisy-chain configuration external clock data read during previous conversion figure 43 shows the detailed timing diagrams for this method. during a conversion, while both cs and rd are low, the result of the previous conversion can be read. the data is shifted out, msb first, with 14 clock pulses, and depending on the sdclk frequency, can be valid on both the falling and rising edges of the clock. the 14 bits have to be read before the current conversion is complete; otherwise, rderror is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. to reduce performance degradation due to digital activity, a fast discontinuous clock of at least 40 mhz is recommended to ensure that all the bits are read during the first half of the sar conversion phase. the daisy-chain feature should not be used in this mode since digital activity occurs during the second half of the sar conversion phase, likely resulting in performance degradation.
ad7951 data sheet rev. a | page 28 of 32 external clock data read after/during conversion it is also possible to begin to read data after conversion and continue to read the last bits after a new conversion has been initiated. this method allows the full throughput and the use of a slower sdclk frequency. again, it is recommended to use a discontinuous sdclk whenever possible to minimize potential incorrect bit decisions. for the different modes, the use of a slower sdclk such as 20 mhz in warp mode, 15 mhz in normal mode and 13 mhz in impulse mode can be used. sdin sdout d0 1 2 3 13 14 busy ext/int = 1 invsclk = 0 cs sdclk 4 d2 d1 15 16 ser/par = 1 rd = 0 12 d13 d12 d11 x13 x12 17 x0 x2 x1 x13 x12 x11 y13 y12 t 31 t 31 x* t 32 t 16 t 33 t 34 t 37 t 35 t 36 *a discontinuous sdclk is recommended. 0 6396-042 figure 42. slave serial data timing for reading (read after convert) sdout d0 123 busy ext/int = 1 invsclk = 0 cs sdclk 13 d1 ser/par = 1 rd = 0 14 d13 d12 t 31 t 31 t 32 t 16 t 37 t 35 t 36 cnvst x* x* x* x* x* x* t 27 *a discontinuous sdclk is recommended. 06396-043 data = sdin figure 43. slave serial data timing for reading (read previous conversion during convert)
data sheet ad7951 rev. a | page 29 of 32 hardware configuration the ad7951 can be configured at any time with the dedicated hardware pins warp, impulse, bipolar, ten, ob/ 2c , and pd for parallel mode (ser/ par = low) or serial hardware mode (ser/ par = high, hw/ sw = high). programming the ad7951 for mode selection and input range configuration can be done before or during conversion. like the reset input, the adc requires at least one acquisition time to settle as indicated in figure 44. see table 6 for pin descriptions. note that these inputs are high impedance when using the software configuration mode. software configuration the pins multiplexed on d[13:10] used for software configura- tion are: hw/ sw , scin, scclk, and sccs . the ad7951 is programmed using the dedicated write-only serial configurable port (scp) for conversion mode, input range selection, output coding, and power-down using the serial configuration register. see table 9 for details of each bit in the configuration register. the scp can only be used in serial software mode selected with ser/ par = high and hw/ sw = low since the port is multiplexed on the parallel interface. the scp is accessed by asserting the ports chip select, sccs , and then writing scin synchronized with scclk, which (like sdclk) is edge sensitive depending on the state of invsclk. see figure 45 for timing details. scin is clocked into the con- figuration register msb first. the configuration register is an internal shift register that begins with bit 8, the start bit. the 9 th sppclk edge updates the register and allows the new settings to be used. as indicated in the timing diagram, at least one acquisition time is required from the 9 th scclk edge. bits [1:0] are reserved bits and are not written to while the scp is being updated. the scp can be written to at any time, up to 40 mhz, and it is recommended to write to while the ad7951 is not busy converting, as detailed in figure 45. in this mode, the full 1 msps is not attainable because the time required for scp access is (t 31 + 9 1/scclk + t 8 ) minimum. if the full throughput is required, the scp can be written to during conversion, however, it is not recommended to write to the scp during the last 450 ns of conversion (busy = high), or performance degradation can result. in addition, the scp can be accessed in both serial master and serial slave read during and read after convert modes. note that at power up, the configuration register is undefined. the reset input clears the configuration register (sets all bits to 0), thus placing the configuration to 0 v to 5 v input, normal mode, and twos complemented output. table 9. configuration register description bit name description 8 start start bit. with the scp enabled ( sccs = low), when start is high, the first rising edge of scclk (invsclk = low) begins to load the register with the new configuration. 7 bipolar input range select. used in conjunction with bit 6, ten, per the following: input range bipolar ten 0 v to 5 v low low 0 v to 10 v low 1 5 v high low 10 v high high 6 ten input range select. see bit 7, bipolar. 5 pd power down. pd = low, normal operation. pd = high power down the adc. the scp is accessible while in power down. to power up the adc, write pd = low on the next configuration setting. 4 impulse mode select. used in conjunction with bit 3, warp, per the following: mode warp impulse normal low low impulse low high warp high low normal high high 3 warp mode select. see bit 4, impulse. 2 ob/ 2c output coding ob/ 2c = low, use twos complement output. ob/ 2c = high, use straight binary output. 1 rsv reserved. 0 rsv reserved. warp, impulse busy hw/sw = 0 cnvst bipolar, ten t 8 ser/par = 0, 1 pd = 0 t 8 0 6396-044 figure 44. hardware configuration timing
ad7951 data sheet rev. a | page 30 of 32 scin s ccl k warp ten 123 67 busy hw/sw = 0 invsclk = 0 cnvst sccs t 8 t 36 t 35 t 37 4 pd 5 bipolar impulse ob/2c x 89 ser/par = 1 bip = 0 or 1 ten = 0 or 1 impulse = 0 or 1 warp = 0 or 1 pd = 0 t 33 t 34 t 31 x t 31 06396-045 start figure 45. serial configuration port timing microprocessor interfacing the ad7951 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. the ad7951 is designed to interface with a parallel 8-bit or 14-bit wide interface, or with a general-purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the ad7951 to prevent digital noise from coupling into the adc. spi interface the ad7951 is compatible with spi and qspi digital hosts and dsps such as blackfin? adsp-bf53x and adsp-218x/adsp-219x. figure 46 shows an interface diagram between the ad7951 and the spi-equipped adsp-219x. to accommodate the slower speed of the dsp, the ad7951 acts as a slave device, and data must be read after conversion. this mode also allows the daisy-chain feature. the convert command could be initiated in response to an internal timer interrupt. the reading process can be initiated in response to the end-of- conversion signal (busy going low) using an interrupt line of the dsp. the serial peripheral interface (spi) on the adsp-219x is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, clock phase bit (cpha) = 1, and spi interrupt enable (timod) = 0 by writing to the spi control register (spicltx). it should be noted that to meet all timing requirements, the spi clock should be limited to 17 mbps, allowing it to read an adc result in less than 1 s. when a higher sampling rate is desired, use one of the parallel interface modes. busy cs sdout sclk cnvst ad7951* pfx spixsel (pfx) misox sckx pfx or tfsx adsp-219x* *additional pins omitted for clarity. dvdd ser/par ext/int rd invsclk 06396-046 figure 46. interfacing the ad7951 to spi interface
data sheet ad7951 rev. a | page 31 of 32 application information layout guidelines while the ad7951 has very good immunity to noise on the power supplies, exercise care with the grounding layout. to facilitate the use of ground planes that can be easily separated, design the printed circuit board that houses the ad7951 so that the analog and digital sections are separated and confined to certain areas of the board. digital and analog ground planes should be joined in only one place, preferably underneath the ad7951, or as close as possible to the ad7951. if the ad7951 is in a system where multiple devices require analog-to-digital ground connections, the connections should still be made at one point only, a star ground point, established as close as possible to the ad7951. to prevent coupling noise onto the die, avoid radiating noise, and to reduce feedthrough: ? do not run digital lines under the device. ? do run the analog ground plane under the ad7951. ? shield fast switching signals, like cnvst or clocks, with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths. ? avoid crossover of digital and analog signals. ? run traces on different but close layers of the board, at right angles to each other, to reduce the effect of feedthrough through the board. the power supply lines to the ad7951 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the impedance of the supplies presented to the ad7951, and to reduce the magnitude of the supply spikes. decoupled ceramic capacitors, typically 100 nf, should be placed on each of the power supplies pins, avdd, dvdd, and ovdd, vcc, and vee. the capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. additionally, low esr 10 f capacitors should be located in the vicinity of the adc to further reduce low frequency ripple. the dvdd supply of the ad7951 can either be a separate supply or come from the analog supply, avdd, or from the digital interface supply, ovdd. when the system digital supply is noisy, or fast switching digital signals are present, and no separate supply is available, it is recommended to connect the dvdd digital supply to the analog supply avdd through an rc filter, and to connect the system supply to the interface digital supply ovdd and the remaining digital circuitry. see figure 27 for an example of this configuration. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. the ad7951 has four different ground pins: refgnd, agnd, dgnd, and ognd. ? refgnd senses the reference voltage and, because it carries pulsed currents, should be a low impedance return to the reference. ? agnd is the ground to which most internal adc analog signals are referenced; it must be connected with the least resistance to the analog ground plane. ? dgnd must be tied to the analog or digital ground plane depending on the configuration. ? ognd is connected to the digital system ground. the layout of the decoupling of the reference voltage is important. to minimize parasitic inductances, place the decoupling capacitor close to the adc and connect it with short, thick traces. evaluating performance a recommended layout for the ad7951 is outlined in the eval-ad7951edz evaluation board documentation. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-ced1z.
ad7951 data sheet rev. a | page 32 of 32 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706-a figure 47. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters compliant to jedec standards mo-220-vkkd-2 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.80 max 0.65 typ 5.50 ref coplanarity 0.08 0.20 ref 1.00 0.85 0.80 0.05 max 0.02 nom seating plane 12 max top view 0.60 max 0.60 max pin 1 indicator 0.50 ref pin 1 indicator 0.25 min 7.10 7.00 sq 6.90 6.85 6.75 sq 6.65 06-05-2012-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. exposed pa d figure 48. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters ordering guide model 1 notes temperature range packag e description package option ad7951bcpz ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-1 AD7951BCPZRL ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-1 ad7951bstz ?40c to +85c 48-lead low prof ile quad flat package [lqfp] st-48 ad7951bstzrl ?40c to +85c 48-lead low prof ile quad flat package [lqfp] st-48 eval-ad7951edz 2 evaluation board eval-ced1z 3 converter evaluation and development board 1 z = rohs compliant part. 2 this board can be used as a standalone evaluation board or in conjunction with the eval-ced1z for evaluation/demonstration pur poses. 3 this board allows a pc to control and communicate with all analog devices evaluation boards ending with the ed designators. ?2006C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06396-0-12/12(a)

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